Computer Architecture

Course Description

CET 4542 – Computer Architecture is a 3-credit, upper-division course in the Computer Engineering Technology taxonomy of Florida's Statewide Course Numbering System (SCNS). The course provides an in-depth study of the structural and functional organization of modern computer systems. Students examine how hardware components — processors, memory subsystems, buses, and I/O interfaces — are designed, interconnected, and optimized for performance. Emphasis is placed on instruction set architecture (ISA) design principles, processor datapath and control, pipelining, memory hierarchy, and emerging parallel and multicore architectures. The course bridges the hardware/software interface and prepares students for careers in computer hardware design, embedded systems, and systems engineering.

This course is typically offered as part of the Bachelor of Applied Science or Bachelor of Science in Computer Engineering Technology and fulfills an upper-division technical requirement. Contact hours: 45 (3 hours lecture per week for 15 weeks).

Learning Outcomes

Required Learning Outcomes

Upon successful completion of this course, students will be able to:

• Explain the fundamental components of a computer system, including the CPU, memory, buses, and I/O subsystems, and describe how each contributes to program execution.
• Analyze and compare Instruction Set Architectures (ISA), including RISC and CISC design philosophies, instruction formats, addressing modes, and the hardware/software interface.
• Design and evaluate single-cycle and multi-cycle processor datapaths and control units, including ALU design and register-file organization.
• Explain the principles of instruction-level pipelining, identify data, structural, and control hazards, and describe forwarding and stall mechanisms used to resolve them.
• Describe the memory hierarchy — including registers, cache (L1/L2/L3), main memory (DRAM), and secondary storage — and analyze performance trade-offs using metrics such as hit rate and average memory access time.
• Explain cache memory organization, including direct-mapped, set-associative, and fully associative designs, along with replacement and write policies.
• Describe the concepts of virtual memory, including address translation, paging, segmentation, page tables, and Translation Lookaside Buffers (TLBs).
• Apply performance evaluation metrics such as CPI (Cycles Per Instruction), clock rate, MIPS, Amdahl's Law, and benchmarking to assess and compare processor designs.
• Describe the organization of input/output (I/O) systems, including programmed I/O, interrupt-driven I/O, and Direct Memory Access (DMA).

Optional Learning Outcomes

Depending on institutional emphasis, students may also be able to:

• Analyze advanced microarchitectural techniques such as superscalar execution, out-of-order execution, branch prediction, and register renaming.
• Compare VLIW (Very Long Instruction Word) and EPIC architectural approaches to instruction-level parallelism.
• Describe multicore and multiprocessor architectures, including cache coherence protocols (e.g., MESI) and shared-memory models.
• Explain the architecture of Graphics Processing Units (GPUs) and their role in data-parallel and high-performance computing workloads.
• Implement or simulate a subset of a processor architecture using a Hardware Description Language (HDL) such as VHDL or Verilog.
• Describe storage system technologies including RAID levels, optical and magnetic disk organization, and bus standards (e.g., PCIe, USB).
• Identify considerations for embedded and real-time systems architecture, including low-power design and microcontroller-based systems.

Major Topics

Required Topics

1. Introduction to Computer Architecture
   • History and evolution of computer systems
   • Von Neumann architecture model
   • Computer performance metrics: CPI, clock rate, MIPS, benchmarks
   • Amdahl's Law and Gustafson's Law
2. Instruction Set Architecture (ISA)
   • Instruction formats and encoding
   • Addressing modes (immediate, register, direct, indirect, displacement)
   • RISC vs. CISC design philosophies
   • Instruction types: data transfer, arithmetic/logic, control flow
   • Representative ISAs: MIPS, RISC-V, x86 overview
3. Processor Datapath and Control
   • ALU design and integer arithmetic
   • Register file organization
   • Single-cycle datapath design
   • Multi-cycle datapath and control signals
   • Hardwired vs. microprogrammed control
4. Pipelining
   • Five-stage pipeline (IF, ID, EX, MEM, WB)
   • Pipeline hazards: structural, data, and control
   • Data forwarding and hazard detection units
   • Branch prediction techniques
   • Pipeline performance analysis
5. Memory Hierarchy and Cache Memory
   • Memory hierarchy levels and locality principles
   • Cache organization: direct-mapped, set-associative, fully associative
   • Cache replacement policies (LRU, FIFO, random)
   • Write policies: write-through and write-back
   • L1, L2, L3 cache performance and trade-offs
6. Virtual Memory
   • Address spaces and address translation
   • Paging and segmentation
   • Page tables and multi-level page tables
   • Translation Lookaside Buffers (TLBs)
   • Page replacement algorithms
7. Input/Output Systems
   • I/O organization and bus architectures
   • Programmed I/O, interrupt-driven I/O, and DMA
   • Bus standards and protocols (e.g., PCIe, USB)
   • I/O performance and bottleneck analysis

Optional Topics

1. Advanced Pipelining and Instruction-Level Parallelism (ILP)
   • Superscalar and out-of-order execution
   • Register renaming and Tomasulo's algorithm
   • VLIW and EPIC architectures
   • Speculative execution techniques
2. Multicore and Parallel Architectures
   • Symmetric multiprocessing (SMP) and shared memory
   • Cache coherence (MESI protocol)
   • SIMD and vector processing
   • GPU architecture overview
3. Storage Systems
   • Magnetic and solid-state disk technology
   • RAID levels and fault tolerance
   • Storage hierarchy and performance
4. Processor Design with HDL
   • Introduction to VHDL or Verilog
   • RTL (Register Transfer Level) design
   • Simulation and synthesis of a simple processor
5. Embedded and Special-Purpose Architectures
   • Microcontroller vs. microprocessor architectures
   • Low-power design considerations
   • DSP and application-specific processors

Resources & Tools

Recommended Textbooks

• Patterson, D. A. & Hennessy, J. L. — Computer Organization and Design: The Hardware/Software Interface (RISC-V or MIPS edition) — Morgan Kaufmann. Industry-standard text used widely across Florida institutions.
• Hennessy, J. L. & Patterson, D. A. — Computer Architecture: A Quantitative Approach — Morgan Kaufmann. Recommended for advanced ILP and parallel architecture topics.
• Null, L. & Lobur, J. — The Essentials of Computer Organization and Architecture — Jones & Bartlett. Commonly used in technology-focused programs.

Software & Simulation Tools

• MARS / SPIM — MIPS assembly language simulators for ISA and datapath exercises
• Ripes — Visual RISC-V pipeline simulator for pipelining and hazard analysis
• Logisim / Logisim Evolution — Digital logic and datapath design simulation
• ModelSim / Vivado — HDL simulation and FPGA synthesis (for optional HDL topics)
• Gem5 — Open-source computer architecture simulator for advanced performance analysis

Career Pathways

Graduates who complete CET 4542 are prepared to pursue the following career areas:

• Computer Hardware Engineer — Design, develop, and test computer processors, circuit boards, and memory devices (Bureau of Labor Statistics SOC 17-2061)
• Embedded Systems Engineer — Develop firmware and low-level software for microcontrollers and SoC platforms in automotive, IoT, and medical devices
• Systems Architect / Solutions Architect — Design high-performance computing systems, server infrastructure, and hardware platforms for enterprise or cloud environments
• FPGA / ASIC Design Engineer — Implement digital logic and custom processor cores using hardware description languages and programmable logic devices
• Computer Engineering Technologist — Support hardware design teams with testing, verification, and integration of processor and memory subsystems
• Graduate Study — CET 4542 fulfills prerequisites for graduate coursework in computer architecture, VLSI design, and high-performance computing at Florida universities (USF, UF, FSU, FAU, UCF)

Special Information

Certification Preparation

The knowledge domains covered in CET 4542 align with and support preparation for the following industry credentials:

• CompTIA A+ — Core 1 domain coverage of CPU architecture, memory types, storage, and I/O interfaces reinforces foundational hardware knowledge addressed in this course.
• CompTIA Server+ — Server hardware architecture, storage subsystems, and I/O management concepts are directly applicable.
• IEEE / ABET Computer Engineering Technology Competencies — Course content maps to ABET CAC program outcomes related to hardware design, systems analysis, and the hardware/software interface.

Articulation and Transfer

As a 4000-level CET course within Florida's SCNS, CET 4542 is designed for upper-division standing and is commonly embedded in Bachelor of Applied Science (B.A.S.) and B.S. in Computer Engineering Technology programs at Florida State Colleges and Universities. Students transferring within the Florida College System should verify equivalency at the receiving institution via the SCNS online database at flscns.fldoe.org.